IRIS Documentation
0.1.1
General
Iris is a simple network simulator for on-chip networks. It is developed at the Computer Architecture and Systems Laboratory, Georgia Institute of Technology.
Iris uses the Discrete Event Simulation methodology. Some of the models it provides:
- An on chip memory controller model with supporting DDR2 and DDR3 delay models
- Switch Arbitor Models
- Routing Techniques
Topologies Supported:
-
Mesh <>
Getting Started: 1. These are the steps to compile the simulator
- ./configure
- make
2. Running the simulator: The simulator takes a configuration file. A sample config is in the config folder [config/generic.cfg]. Some of the configuration parameters may also be passed at the command line. Some of these options are listed here and others are documented in detail in the sample config file. ./simMc2Mesh config/generic.cfg
- for varying address mapping The bit positions of the address to be used to select the MC id can be specified at command line with switch --mc_bits [eg. --mc_bits 10] For distributing the address space among threads. The command line switch --thread_id_bits may be used
-routing algorithms Various routing algorithms may be selected at command line with the switch --routing_scheme [Eg. --routing_scheme xy]
-switch arbitration Various switch arbitration schemes may be selected at command line with the switch --sw_arbitration [Eg, --sw_arbitration round-robin]
Switches may be added. For examples on how to add switches and use them follow the code in source/frontend/impl/simMc2Mesh.cc
Environment details: -------------------
The current version has been tested with 1. gcc version 4.3.3 (Ubuntu 4.3.3-5ubuntu4) Linux 2.6.28-18-generic #60-Ubuntu SMP i686 GNU/Linux 2. gcc version 4.2.4 (Ubuntu 4.2.4-1ubuntu4) Linux 2.6.24-23-generic #1 SMP i686 GNU/Linux
