mc_constants.h

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00001 /*
00002  * =====================================================================================
00003  *
00004  *       Filename:  constants.h
00005  *
00006  *    Description:  
00007  *
00008  *        Version:  1.0
00009  *        Created:  02/25/2010 11:18:28 PM
00010  *       Revision:  none
00011  *       Compiler:  gcc
00012  *
00013  *         Author:  SYED MINHAJ HASSAN
00014  *        Company:  Georgia Institute of Technology
00015  *
00016  * =====================================================================================
00017  */
00018 #ifndef _CONSTANTS_H
00019 #define _CONSTANTS_H
00020 #include <math.h>
00021 #include <stdint.h>
00022 
00023 //#define DEBUG
00024 //#define DEEP_DEBUG
00025 
00026 typedef unsigned long long int Time;
00027 typedef unsigned long long int Addr_t;
00028 typedef unsigned int uint;
00029 typedef unsigned int UInt;
00030 
00031 
00039 #ifndef USE_ZESTO
00040 enum cache_command { CACHE_NOP, CACHE_READ, CACHE_WRITE, CACHE_WRITEBACK, CACHE_PREFETCH, REFRESH, INVALIDATE, FWD_DIRTY, READ_RESPONSE, WRITE_RESPONSE, ACK };
00041 #else
00042 #include "../zesto/zesto-cache.h"
00043 #endif
00044    enum DRAM_PAGE_POLICY { OPEN_PAGE_POLICY, CLOSE_PAGE_POLICY};
00045    enum MC_SCHEDULLING_ALGO { PAR_BS, FR_FCFS, FC_FS, NFQ};
00046    enum ADDR_MAP_SCHEME { PAGE_INTERLEAVING, PERMUTATION, CACHELINE_INTERLEAVING, SWAPPING, GENERIC, NO_SCHEME, LOCAL_ADDR_MAP};
00047    enum DRAM_CONFIG { DDR3_1333_9, 
00048     DDR3_1600_10,
00049     DDR3_1333_6,
00050     DDR2_533_4,
00051     DDR2_667_4
00052 };
00053 extern DRAM_PAGE_POLICY dram_page_policy; 
00054 extern MC_SCHEDULLING_ALGO mc_scheduling_algorithm;
00055 extern ADDR_MAP_SCHEME addr_map_scheme;
00056 
00057 extern uint NO_OF_THREADS; 
00058 extern uint NO_OF_CHANNELS ;            //  (int)log2() = k bits. 
00059 extern uint NO_OF_RANKS ;                       //  (int)log2() = l bits.
00060 extern uint NO_OF_BANKS ;                       //  (int)log2() = b bits. 
00061 #define NO_OF_BUFFERS NO_OF_BANKS
00062 extern uint NO_OF_ROWS;                 //4096 //  (int)log2() = r bits. 
00063 extern uint NO_OF_COLUMNS;           //  (int)log2() = c bits. 
00064 extern uint COLUMN_SIZE ;               //  (int)log2() = v bits.  Column Size = 2bytes
00065 #define BLOCKS_PER_ROW 128              //  (int)log2() = n bits.  Cache line Per Row
00066 #define CACHE_BLOCK_SIZE 64             //  (int)log2() = z bits.  L2 Cache Block Size
00067 #define ROW_SIZE NO_OF_COLUMNS*COLUMN_SIZE //(Also equal to BLOCKS_PER_ROW*CACHE_BLOCK_SIZE)
00068 #define DRAM_SIZE NO_OF_CHANNELS*NO_OF_RANKS*NO_OF_BANKS*NO_OF_ROWS*ROW_SIZE
00069 #define TAG_BITS 8                      // t bits
00070 
00071 #define USE_MSHR 1 
00072 extern uint MSHR_SIZE ; 
00073 
00074 //#define CORE_UNCORE_RATIO 1
00075 extern uint MAX_BUFFER_SIZE ;
00076 extern uint MAX_CMD_BUFFER_SIZE ;
00077 extern uint RESPONSE_BUFFER_SIZE ; //(NO_OF_CHANNELS * (NO_OF_BANKS*NO_OF_RANKS*MAX_BUFFER_SIZE + MAX_CMD_BUFFER_SIZE)) / 4  // Size = Upper Limit / 2
00078 
00079 #define BATCH_FORM_TIME 2000;
00080 #define MAX_BATCH_SIZE 5
00081 #define MAX_READ_OV_WRITE 8
00082 
00083 extern uint NETWORK_ADDRESS_BITS ;
00084 extern uint NETWORK_THREADID_BITS ;
00085 extern uint NETWORK_COMMAND_BITS ; 
00086 
00087 #define READ_SIZE CACHE_BLOCK_SIZE
00088 #define WRITE_SIZE CACHE_BLOCK_SIZE
00089 #define PREFETCH_SIZE CACHE_BLOCK_SIZE
00090 #define WRITEBACK_SIZE CACHE_BLOCK_SIZE
00091 
00092 #define REFRESH_PERIOD CORE_SPEED*64000                 // 64ms
00093 #define REFRESH_INC (ullint)floor(REFRESH_PERIOD/(8192)) - BUS_CYCLE    // -1 BUS_CYCLE to be on the safe side
00094 /* 
00095 extern uint NO_OF_THREADS;
00096 extern uint NO_OF_CHANNELS;             //  (int)log2() = k bits. 
00097 extern uint NO_OF_RANKS;                //  (int)log2() = l bits.
00098 extern uint NO_OF_BANKS;                //  (int)log2() = b bits. 
00099 extern uint NO_OF_BUFFERS;
00100 extern uint NO_OF_ROWS;                 //4096 //  (int)log2() = r bits. 
00101 extern uint NO_OF_COLUMNS;              //  (int)log2() = c bits. 
00102 extern uint COLUMN_SIZE;                        //  (int)log2() = v bits.  Column Size = 2bytes
00103 extern uint BLOCKS_PER_ROW;             //  (int)log2() = n bits.  Cache line Per Row
00104 extern uint CACHE_BLOCK_SIZE;           //  (int)log2() = z bits.  L2 Cache Block Size
00105 extern uint ROW_SIZE;
00106 extern uint DRAM_SIZE;
00107 #define TAG_BITS 8                      // t bits
00108 
00109 #define USE_MSHR 1 
00110 extern uint MSHR_SIZE;
00111 
00112 extern uint MAX_BUFFER_SIZE;
00113 extern uint MAX_CMD_BUFFER_SIZE;
00114 extern uint RESPONSE_BUFFER_SIZE;  //(NO_OF_CHANNELS * (NO_OF_BANKS*NO_OF_RANKS*MAX_BUFFER_SIZE + MAX_CMD_BUFFER_SIZE)) / 4  // Size = Upper Limit / 2
00115 
00116 #define BATCH_FORM_TIME 2000;
00117 //#define MAX_BATCH_TIME 2000;
00118 #define MAX_BATCH_SIZE 5
00119 #define MAX_READ_OV_WRITE 8
00120 
00121 extern uint NETWORK_ADDRESS_BITS;
00122 extern uint NETWORK_THREADID_BITS;
00123 extern uint NETWORK_COMMAND_BITS; 
00124 
00125 #define READ_SIZE CACHE_BLOCK_SIZE
00126 #define WRITE_SIZE CACHE_BLOCK_SIZE
00127 #define PREFETCH_SIZE CACHE_BLOCK_SIZE
00128 #define WRITEBACK_SIZE CACHE_BLOCK_SIZE
00129 
00130 
00131 #define REFRESH_PERIOD CORE_SPEED*64000                 // 64ms
00132 #define REFRESH_INC (ullint)floor(REFRESH_PERIOD/(8192)) - BUS_CYCLE    // -1 BUS_CYCLE to be on the safe side
00133  * */
00134 
00135 extern float CORE_SPEED;
00136 extern float CYCLE_2_NS;
00137 
00138 extern unsigned int DDR_BUS_WIDTH;
00139 extern float BUS_SPEED;
00140 extern float MEM_SPEED;
00141 extern float MEM_CYCLE;
00142 extern float BUS_CYCLE;
00143 extern float CYCLE_2_NS;
00144 extern float tREFI;
00145 extern float tRFC;
00146 extern float tRC;
00147 extern float tRAS;
00148 extern unsigned int t_CMD;
00149 extern unsigned int t_RCD;
00150 extern unsigned int t_RRD;
00151 extern unsigned int t_RAS;
00152 extern unsigned int t_CAS;
00153 extern unsigned int t_RTRS;
00154 extern unsigned int t_OST;
00155 extern unsigned int t_WR;
00156 extern unsigned int t_WTR;
00157 extern unsigned int t_RP;
00158 extern unsigned int t_CCD;
00159 extern unsigned int t_AL;
00160 extern unsigned int t_CWD;
00161 extern unsigned int t_RC;
00162 extern unsigned int t_RTP;
00163 extern unsigned int t_RFC;
00164 
00165 #endif
00166 

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