GenericRouter4Stg Class Reference

#include <genericRouter4Stg.h>

Inheritance diagram for GenericRouter4Stg:

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List of all members.

Public Member Functions

 GenericRouter4Stg ()
 ~GenericRouter4Stg ()
void init (uint ports, uint vcs, uint credits, uint buffer_size)
void set_no_nodes (uint nodes)
 These functions are mainly for DOR routing and are seperated so as to not force DOR modelling in all designs.
void set_grid_x_location (uint a, uint b, uint c)
void set_grid_y_location (uint a, uint b, uint c)
void send_credit_back (uint i)
void process_event (IrisEvent *e)
string toString () const
string print_stats ()
void set_edge_links ()
void dump_buffer_state ()

Public Attributes

vector< vector< uint > > downstream_credits
uint packets
uint flits
double total_packet_latency
double last_flit_out_cycle
unsigned long long int stat_sim_total_time
vector< vector< uint > > stat_packet_out
vector< vector< uint > > stat_flit_out
bool is_mc_router

Private Member Functions

void handle_link_arrival_event (IrisEvent *e)
 Event handle for the LINK_ARRIVAL_EVENT event. Entry from DES kernel.
void handle_tick_event (IrisEvent *e)
 Event handle for the TICK_EVENT. Entry from DES kernel.
void handle_detect_deadlock_event (IrisEvent *)
void do_switch_traversal ()
void do_switch_allocation ()

Private Attributes

vector< GenericBufferin_buffers
vector< GenericRCdecoders
vector< InputBufferStateinput_buffer_state
GenericVcAllocator vca
PToPSwitchArbiterVcs swa
GenericCrossbar xbar
vector< uintavailable_ports
vector< uintavailable_vcs
vector< vector< uint > > cr_time
bool ticking


Detailed Description

===================================================================================== Class: Description: Implementing a generic 4 stage physical router model BW->RC->VCA->SA->ST->LT Buffer write(BW) Route Computation (RC) Virtual Channel Allocation (VCA) Switch Allocation (SA) Switch Traversal (ST) Link Traversal (LT)

Model Description in cycles: --------------------------- BW and RC stages happen in the same cycle ( BW pushes the flits into the input buffer and the RC unit. ) VCA: Head flits request for an output virtual channel and max(pxv) requesting input ports/vcs. On winning the grant the packet requests for SA. The winner is cleared when the tail exits. SA: Pick one output port from n requesting input ports (0<n<p) for the pxp crossbar ST: Move the flits across the crossbar and push it out on the link LT: This is not modelled within the router and is part of the link component. =====================================================================================

Definition at line 67 of file genericRouter4Stg.h.


Constructor & Destructor Documentation

GenericRouter4Stg::GenericRouter4Stg (  ) 

Definition at line 24 of file genericRouter4Stg.cc.

References NetworkComponent::name, and ticking.

GenericRouter4Stg::~GenericRouter4Stg (  ) 

constructor

Definition at line 30 of file genericRouter4Stg.cc.


Member Function Documentation

void GenericRouter4Stg::do_switch_allocation (  )  [private]

void GenericRouter4Stg::do_switch_traversal (  )  [private]

void GenericRouter4Stg::dump_buffer_state (  ) 

void GenericRouter4Stg::handle_detect_deadlock_event ( IrisEvent e  )  [private]

Definition at line 148 of file genericRouter4Stg.cc.

References _DBG_NOARG, cr_time, DETECT_DEADLOCK_EVENT, input_buffer_state, Simulator::Now(), Router::ports, NetworkComponent::process_event(), Simulator::Schedule(), IrisEvent::type, and Router::vcs.

Referenced by process_event().

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void GenericRouter4Stg::handle_link_arrival_event ( IrisEvent e  )  [private]

void GenericRouter4Stg::handle_tick_event ( IrisEvent e  )  [private]

Event handle for the TICK_EVENT. Entry from DES kernel.

Body and tail flits get written in link arrival and since the message state may already been pushed to ST because of the header we want to ensure that all flits go thru an IB and ST stage. Hence ST is done on the flits_in_ib information and not buffer occupancy. for( uint i=0; i<(ports*vcs); i++) { uint ip = input_buffer_state[i].input_port; uint ic = input_buffer_state[i].input_channel;

if ((input_buffer_state[i].pipe_stage == SW_TRAVERSAL || input_buffer_state[i].pipe_stage == IB ) && (input_buffer_state[i].flits_in_ib < in_buffers[ip].get_occupancy(ivc))) { input_buffer_state[i].flits_in_ib++; ticking = true; } }

Definition at line 606 of file genericRouter4Stg.cc.

References Router::credits, GenericVcAllocator::current_winners, do_switch_allocation(), do_switch_traversal(), downstream_credits, FULL, IB, in_buffers, input_buffer_state, GenericVcAllocator::is_empty(), GenericVcAllocator::is_requested(), istat, NetworkComponent::node_ip, Simulator::Now(), GenericVcAllocator::pick_winner(), Router::ports, NetworkComponent::process_event(), GenericVcAllocator::request(), PToPSwitchArbiterVcs::request(), Simulator::Schedule(), GenericVcAllocator::squash_requests(), IrisStats::stat_router, SW_TRAVERSAL, swa, SWA_REQUESTED, TICK_EVENT, ticking, IrisEvent::vc, vca, VCA_COMPLETE, VCA_REQUESTED, and Router::vcs.

Referenced by process_event().

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void GenericRouter4Stg::init ( uint  ports,
uint  vcs,
uint  credits,
uint  buffer_size 
) [virtual]

string GenericRouter4Stg::print_stats ( void   )  [virtual]

void GenericRouter4Stg::process_event ( IrisEvent e  )  [virtual]

void GenericRouter4Stg::send_credit_back ( uint  i  ) 

void GenericRouter4Stg::set_edge_links (  ) 

void GenericRouter4Stg::set_grid_x_location ( uint  a,
uint  b,
uint  c 
) [virtual]

For DOR the no of nodes in the network and the grid sizes are to be set and passed to RC.

Implements Router.

Definition at line 113 of file genericRouter4Stg.cc.

References decoders.

void GenericRouter4Stg::set_grid_y_location ( uint  a,
uint  b,
uint  c 
) [virtual]

Implements Router.

Definition at line 119 of file genericRouter4Stg.cc.

References decoders.

void GenericRouter4Stg::set_no_nodes ( uint  nodes  )  [virtual]

These functions are mainly for DOR routing and are seperated so as to not force DOR modelling in all designs.

Initialise the router for ports, vcs and credits. TODO buffer size not used right now. Just make sure its larger than credits.

Implements Router.

Definition at line 103 of file genericRouter4Stg.cc.

References decoders.

string GenericRouter4Stg::toString (  )  const [virtual]

Reimplemented from Router.

Definition at line 782 of file genericRouter4Stg.cc.

References NetworkComponent::address, decoders, in_buffers, NetworkComponent::node_ip, swa, GenericCrossbar::toString(), PToPSwitchArbiterVcs::toString(), and xbar.

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Member Data Documentation

Definition at line 111 of file genericRouter4Stg.h.

Definition at line 112 of file genericRouter4Stg.h.

vector< vector<uint> > GenericRouter4Stg::cr_time [private]

Definition at line 94 of file genericRouter4Stg.h.

Referenced by handle_link_arrival_event(), init(), and print_stats().

Definition at line 100 of file genericRouter4Stg.h.

Referenced by do_switch_traversal(), and handle_link_arrival_event().

Definition at line 96 of file genericRouter4Stg.h.

Referenced by do_switch_traversal(), and print_stats().

These are the statistics variables

Definition at line 93 of file genericRouter4Stg.h.

Referenced by handle_link_arrival_event(), init(), and print_stats().

Definition at line 99 of file genericRouter4Stg.h.

Referenced by do_switch_traversal(), init(), and print_stats().

Definition at line 98 of file genericRouter4Stg.h.

Referenced by do_switch_traversal(), init(), and print_stats().

Definition at line 97 of file genericRouter4Stg.h.

Definition at line 95 of file genericRouter4Stg.h.

Referenced by do_switch_traversal(), init(), and print_stats().

Definition at line 108 of file genericRouter4Stg.h.

Referenced by do_switch_traversal(), handle_tick_event(), and init().

Definition at line 110 of file genericRouter4Stg.h.

Referenced by do_switch_allocation(), do_switch_traversal(), init(), and toString().


The documentation for this class was generated from the following files:

Generated on Tue Oct 19 17:22:16 2010 for IRIS by  doxygen 1.5.8