00001 /* 00002 * ===================================================================================== 00003 * 00004 * Filename: routerReqReply.h 00005 * 00006 * Description: Implementing a generic virtual channel router that can 00007 * handle request and reply messages. 00008 * 00009 * Version: 1.0 00010 * Created: 03/11/2010 08:56:06 PM 00011 * Revision: none 00012 * Compiler: gcc 00013 * 00014 * Author: Mitchelle Rasquinha (), mitchelle.rasquinha@gatech.edu 00015 * Company: Georgia Institute of Technology 00016 * 00017 * ===================================================================================== 00018 */ 00019 00020 #ifndef _routerReqReply_h_INC 00021 #define _routerReqReply_h_INC 00022 00023 #include "../interfaces/router.h" 00024 #include "genericBuffer.h" 00025 #include "genericRC.h" 00026 #include "vcaMsgAware.h" 00027 //#include "pvtopv_swa.h" 00028 #include "genericVcAllocator.h" 00029 #include "ptopSwaVcs.h" 00030 #include "genericCrossbar.h" 00031 #include "../../../util/genericData.h" 00032 #include "../../../util/stats.h" 00033 #include "genericLink.h" 00034 #include <sys/time.h> 00035 #include <algorithm> 00036 #include <list> 00037 00038 extern uint send_early_credit; 00039 extern uint stat_print_level; 00040 extern uint do_two_stage_router; 00041 extern uint no_msg_classes; 00042 extern void print_state_at_deadlock(void); 00043 extern IrisStats* istat; 00044 00045 class RouterReqReply: public Router 00046 { 00047 public: 00048 RouterReqReply (); 00049 ~RouterReqReply(); 00050 void init(uint ports, uint vcs, uint credits, uint buffer_size); 00054 void set_no_nodes( uint nodes); 00057 void set_grid_x_location ( uint a, uint b, uint c); 00058 void set_grid_y_location ( uint a, uint b, uint c); 00059 00060 void send_credit_back( uint i); 00061 00062 void process_event(IrisEvent* e); 00063 string toString() const; 00064 string print_stats(); 00065 void set_edge_links(); 00066 vector< vector<uint> > downstream_credits; 00067 void dump_buffer_state(); 00068 00069 00070 protected: 00071 00072 private: 00073 vector <GenericBuffer> in_buffers; 00074 vector <GenericRC> decoders; 00075 vector <InputBufferState> input_buffer_state; 00076 VcaMsgAware vca; 00077 vector< vector< uint> > sw_alloc; 00078 vector< vector <uint> >request_op; 00079 vector <uint> available_ports; 00080 vector <uint> available_vcs; 00081 vector < vector<uint> > cr_time; 00082 00083 bool ticking; 00084 void handle_link_arrival_event(IrisEvent* e); 00085 void handle_tick_event(IrisEvent* e); 00086 void handle_detect_deadlock_event(IrisEvent*); 00087 void do_switch_traversal(); 00088 void do_switch_allocation(); 00089 void do_input_buffering(); 00090 void do_virtual_channel_allocation(); 00091 void request_switch_allocation(); 00092 00094 double stat_buffer_occupancy; 00095 uint stat_packets; 00096 uint stat_flits; 00097 double stat_total_packet_latency; 00098 double last_flit_out_cycle; /* indicates the last active cycle for the router */ 00099 double stat_swa_fail_msg_ratio; 00100 double stat_swa_load; 00101 double stat_vca_fail_msg_ratio; 00102 double stat_vca_load; 00103 ullint stat_sim_total_time; 00104 vector< vector<uint> > stat_packet_out; 00105 vector< vector<uint> > stat_flit_out; 00106 bool is_mc_router; 00107 ullint stat_ib_cycles; 00108 ullint stat_rc_cycles; 00109 ullint stat_vca_cycles; 00110 ullint stat_swa_cycles; 00111 ullint stat_st_cycles; 00112 00113 }; /* ----- end of class RouterReqReply ----- */ 00114 00115 #endif /* ----- #ifndef _routerReqReply_h_INC ----- */ 00116
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